? semiconductor components industries, llc, 2011 february, 2011 ? rev. 1 1 publication order number: NCP5911/d NCP5911 imvp7.0 compatible synchronous buck mosfet driver the NCP5911 is a high performance dual mosfet gate driver optimized to drive the gates of both high ? side and low ? side power mosfets in a synchronous buck converter. it can drive up to 3 nf load with a 25 ns propagation delay and 20 ns transition time. adaptive anti ? cross ? conduction and power saving operation circuit can provide a low switching loss and high efficiency solution for notebook systems. a bidirectional enable pin can provide a fault signal to the controller when the gate driver detects an undervoltage lockout. the uvlo function guarantees the outputs are low when the supply voltage is low. features ? faster rise and fall times ? adaptive anti ? cross ? conduction circuit ? zero cross detection function ? output disable control turns off both mosfets ? undervoltage lockout ? power saving operation under light load conditions ? direct interface to ncp6131 and other compatible pwm controllers ? thermally enhanced package ? these devices are pb ? free and are rohs compliant* typical applications ? power management solutions for notebook systems *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. device package shipping ? ordering information NCP5911mntbg dfn8 (pb ? free) 3000 / tape & reel dfn8 case 506aa marking diagram http://onsemi.com ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. al = specific device code m = date code = pb ? free package 1 2 3 4 5 6 7 8 bst pwm sw vcc en drvh drvl gnd pinout diagram (note: microdot may be in either location) flag 9 alm 1 1
NCP5911 http://onsemi.com 2 bst pwm logic drvh sw anti ? cross conduction vcc drvl vcc en fault uvlo zcd detection figure 1. block diagram pin descriptions pin no. symbol description 1 bst floating bootstrap supply pin for high side gate driver. connect the bootstrap capacitor between this pin and the sw pin. 2 pwm control input. the pwm signal has three distinctive states: low = low side fet enabled, mid = diode emulation enabled, high = high side fet enabled. 3 en logic input. a logic high to enable the part and a logic low to disable the part. three states logic input: en = high to enable the gate driver; en = low to disable the driver; en = mid to go into diode mode (both high and low side gate drive signals are low) 4 vcc power supply input. connect a bypass capacitor (0.1 f) from this pin to ground. 5 drvl low side gate drive output. connect to the gate of low side mosfet. 6 gnd bias and reference ground. all signals are referenced to this node. 7 sw switch node. connect this pin to the source of the high side mosfet and drain of the low side mosfet. 8 drvh high side gate drive output. connect to the gate of high side mosfet. 9 flag thermal flag. there is no electrical connection to the ic. connect to ground plane.
NCP5911 http://onsemi.com 3 application circuit figure 2. application circuit vreg_sw1_hg vccp tp3 vreg_sw1_out vreg_sw1_lg tp6 tp7 tp8 tp4 tp1 tp2 tp5 ntmfs4851n ntmfs4851n q9 q10 ntmfs4821n q1 NCP5911 bst pwm en vcc hg sw gnd lg pad dron pwm csn11 csp11 c1 c2 c3 ce9 l r3 c6 r164 5v_power r1 r143 c4 0.027uf 0.0 1.02 c5 1uf r142 0.0 0.0 2.2 2700pf 235nh 4.7uf 4.7uf 4.7uf 390uf + jp13_etch jp14_etch vin
NCP5911 http://onsemi.com 4 absolute maximum ratings electrical information symbol pin name v max v min v cc main supply voltage input 6.5 v ? 0.3 v bst bootstrap supply voltage 35 v wrt/ gnd 40 v 50 ns wrt/ gnd 6.5 v wrt/ sw ? 0.3 v wrt/sw sw switching node (bootstrap supply return) 35 v 40 v 50 ns ? 5 v ? 10 v (200 ns) drvh high side driver output bst + 0.3 v ? 0.3 v wrt/sw ? 2 v (< 200 ns) wrt/sw drvl low side driver output v cc + 0.3 v ? 0.3 v dc ? 5 v (< 200 ns) pwm drvh and drvl control input 6.5 v ? 0.3 v en enable pin 6.5 v ? 0.3 v gnd ground 0 v 0 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. *all signals referenced to agnd unless noted otherwise. thermal information symbol parameter value unit r ja thermal characteristic qfn package (note 1) 119 c/w t j operating junction temperature range (note 2) 0 to 150 c t a operating ambient temperature range ? 40 to +100 c t stg maximum storage temperature range ? 55 to +150 c msl moisture sensitivity level ? qfn package 1 *the maximum package power dissipation must be observed. 1. 1 in 2 cu, 1 oz. thickness. 2. jesd 51 ? 7 (1s2p direct ? attach method) with 1 lfm.
NCP5911 http://onsemi.com 5 NCP5911 electrical characteristics ( ? 40 c < t a < +100 c; 4.5 v < v cc < 5.5 v, 4.5 v < bst ? swn < 5.5 v, 4.5 v < bst < 30 v, 0 v < swn < 21 v, unless otherwise noted) parameter test conditions min typ max unit supply voltage vcc operation voltage 4.5 5.5 v undervoltage lockout vcc start threshold 3.8 4.35 4.5 v vcc uvlo hysteresis 150 200 250 mv supply current shutdown mode i cc + i bst , en = gnd 15 30 a normal mode i cc + i bst , en = 5 v, pwm = osc 5.0 ma standby current i cc + i bst , en = high, pwm = low, no loading on drvh & drvl 0.9 ma standby current i cc + i bst , en = high, pwm = high, no loading on drvh & drvl 1.1 ma bootstrap diode forward voltage v cc = 5 v, forward bias current = 2 ma 0.1 0.4 0.6 v pwm input pwm input high 3.4 v pwm mid ? state 1.3 2.7 v pwm input low 0.7 v zcd blanking timer 350 ns high side driver output impedance, sourcing current v bst ? v sw = 5 v 0.9 2.0 output impedance, sinking current v bst ? v sw = 5 v 0.7 2.0 drvh rise time tr drvh v cc = 5 v, 3 nf load, v bst ? v sw = 5 v 16 25 ns drvh fall time tf drvh v cc = 5 v, 3 nf load, v bst ? v sw =5 v 11 18 ns drvh turn ? off propagation delay tpdl drvh c load = 3 nf 10 30 ns drvh turn ? on propagation delay tpdh drvh c load = 3 nf 15 45 ns sw pulldown resistance sw to pgnd 45 k drvh pulldown resistance drvh to sw, bst ? sw = 0 v 45 k low side driver output impedance, sourcing current 0.9 2.0 output impedance, sinking current 0.4 1.0 drvl rise time tr drvl c load = 3 nf 16 25 ns drvl fall time tf drvl c load = 3 nf 11 15 ns drvl turn ? off propagation delay tpdl drvl c load = 3 nf 10 30 ns drvl turn ? on propagation delay tpdh drvl c load = 3 nf 5.0 25 ns drvl pulldown resistance drvl to pgnd, v cc = pgnd 45 k
NCP5911 http://onsemi.com 6 NCP5911 electrical characteristics ( ? 40 c < t a < +100 c; 4.5 v < v cc < 5.5 v, 4.5 v < bst ? swn < 5.5 v, 4.5 v < bst < 30 v, 0 v < swn < 21 v, unless otherwise noted) parameter unit max typ min test conditions en input input voltage high 3.3 v input voltage mid 1.35 1.8 v input voltage low 0.6 v input bias current ? 1.0 1.0 a fault mode enable pin pulldown current 4.0 30 ma propagation delay time 20 40 ns sw node sw node leakage current 20 a zero cross detection threshold voltage ? 6.0 mv
NCP5911 http://onsemi.com 7 table 1. decoder truth table input zcd drvl drvh pwm high (enable high) zcd reset low high pwm mid (enable high) positive current through the inductor high low pwm mid (enable high) zero current through the inductor low low pwm low (enable high) zcd reset high low enable at mid x low low figure 3. figure 4. timing diagram pwm drvh ? sw drvl il 1v 1v
NCP5911 http://onsemi.com 8 application information the NCP5911 gate driver is a single phase mosfet driver designed for driving n ? channel mosfets in a synchronous buck converter topology. the NCP5911 is designed to work with on semiconductor?s ncp6131 multi ? phase controller. this gate driver is optimized for notebook applications. undervoltage lockout drvh and drvl are held low until v cc reaches 4.5 v during startup. the pwm signal will control the gate status when v cc threshold is exceeded. three ? state en signal undervoltage lockout will de ? assert the en pin, which will pull down the dron pin of the controller as well. when en is set to the mid state, both drvh and drvl are set low, to force diode mode operation. pwm input and zero cross detect (zcd) the pwm input, along with en and zcd, control the state of drvh and drvl. when pwm is set high, drvh will be set high after the adaptive non ? overlap delay. when pwm is set low, drvl will be set high after the adaptive non ? overlap delay. when pwm is set to the mid state, drvh will be set low, and after the adaptive non ? overlap delay, drvl will be set high. drvl remains high during the zcd blanking time. when the timer has expired, the sw pin will be monitored for zero cross detection. after the detection, drvl will be set low. adaptive non ? overlap adaptive dead time control is used to avoid shoot ? through damage of the power mosfets. when the pwm signal pulls high, drvl will be set low and the driver will monitor the gate voltage of the low side mosfet. when the drvl voltage falls below the gate threshold, drvh will be set to high after the tpdh drvh delay. when pwm is set low, the driver will monitor the gate voltage of the high side mosfet. when the drvh ? swn voltage falls below the top gate drive threshold, drvl will be set to high after the tpdh drvl delay. layout guidelines the layout for a dc ? dc converter is very important. the bootstrap and v cc bypass capacitors should be placed close to the driver ic. connect the gnd pin to a local ground plane. the ground plane can provide a good return path for gate drives and reduce the ground noise. the thermal slug should be tied to the ground plane for good heat dissipation. to minimize the ground loop for the low side mosfet, the driver gnd pin should be close to the low ? side mosfet source pin. the gate drive trace should be routed to minimize its length. the minimum width is 20 mils. gate driver power loss calculation the gate driver power loss consists of the gate drive loss and quiescent power loss. the equation below can be used to calculate the power dissipation of the gate driver. q gmf is the total gate charge for each main mosfet and q gsf is the total gate charge for each synchronous mosfet. p drv (eq. 1) f sw 2 n n mf q gmf n sf q gsf i cc v cc also shown is the standby dissipation factor (i cc x v cc ) of the driver.
NCP5911 http://onsemi.com 9 package dimensions dfn8 2x2 case 506aa ? 01 issue e ??? ??? a d e b c 0.15 pin one 2x reference 2x top view side view bottom view a l (a3) d2 e2 c c 0.15 c 0.10 c 0.08 note 4 a1 seating plane e/2 e 8x k note 3 b 8x 0.10 c 0.05 c a b b dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.20 0.30 d 2.00 bsc d2 1.10 1.30 e 2.00 bsc e2 0.70 0.90 e 0.50 bsc k l 0.25 0.35 1 4 8 5 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 2.30 0.50 0.50 8x dimensions: millimeters 0.30 pitch 8x 1 package outline recommended l1 detail a l optional constructions l ??? 0.10 0.30 ref 0.90 1.30 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NCP5911/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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